  0 PAK 68/3, GAL U2:  Cache Control Logic, L2-Cache über Jumper schaltbar
  1 08-09-93   V2_JPa     Holger Zimmermann @ PE
  2 %ID
  3       P2_JP
  4 %TYP
  5       GAL20V8A
  6 %PINS
  7  !rom  mat2  a0  a1  !as_00  !bgack_20  !wr  !as_20       !dsack  !reset  siz1
  8  siz0  !dram  !twe2  !dwe3  !dwe1  !c2off  !dwe2  !tclr  
     !dwe0  !twe0  mat0
  9 %LOGIC
 10 
 11  dwe0.OE = VCC;
 12  dwe0  = dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * !a0
 13        + dram * !tclr * as_20 *  as_00 * !wr * !mat0 * !a1 * dsack
 14        + dram * !tclr * as_20 *  as_00 * !wr *  dwe0 * !a1 * dsack;
 15 
 16  dwe1  = dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * siz1
 17        + dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * a0
 18        + dram * !tclr * as_20 *  as_00 *  wr *  mat0 * !a1 * !siz0
 19        + dram * !tclr * as_20 *  as_00 * !wr * !mat0 * !a1 * dsack
 20        + dram * !tclr * as_20 *  as_00 * !wr *  dwe1 * !a1 * dsack;
 21 
 22  dwe2  = dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * !a0
 23        + dram * !tclr * as_20 *  as_00 * !wr * !mat2 *  a1 * dsack
 24        + dram * !tclr * as_20 *  as_00 * !wr *  dwe2 *  a1 * dsack;
 25 
 26  dwe3  = dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * siz1
 27        + dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * a0
 28        + dram * !tclr * as_20 *  as_00 *  wr *  mat2 *  a1 * !siz0
 29        + dram * !tclr * as_20 *  as_00 * !wr * !mat2 *  a1 * dsack
 30        + dram * !tclr * as_20 *  as_00 * !wr *  dwe3 *  a1 * dsack;
 32  twe0  = dram * !tclr * as_20 *  as_00 * !wr *  dwe0 * !a1 * dsack
 33        + dram * !tclr * as_20 *  as_00 * !wr *  dwe1 * !a1 * dsack;
 34 
 35  twe2  = dram * !tclr * as_20 *  as_00 * !wr *  dwe2 *  a1 * dsack
 36        + dram * !tclr * as_20 *  as_00 * !wr *  dwe3 *  a1 * dsack;
 37 
 38  tclr  =  as_20 * tclr
 39        + !as_20 * bgack_20
 40        + !as_20 * reset
 41        + !as_20 * c2off;
 42 
 43  c2off.OE = GND;                                  ´SLC off per Jumper
 44 
 45 %END